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Showing posts from February, 2019

STM32 USART Pt. 2 : Interrupts

In the previous post I showed you guys how to setup the USART in its most basic mode which is UART with no interrupts. In this second part I will explain the register bits and relevant code to configure the UART in interrupt mode. Interrupt allows for non-blocking reception and transmission of our data. Our program is free to do other task and not concern itself with the constant polling of the status register. 




Control Register 1: From the previous post you will recall the Control Register 1. Whip out your datasheet and take a look or just follow along here. Below you see a screenshot of CR1 and I have highlighted the relevant bit that we must set to enable desired interrupts. TXEIE   : TX Empty Interrupt Enable: By enabling this bit we will get an interrupts when the TX buffer, in other words the data register, is empty.TCIE     : Transfer Complete Interrupt Enable: This will generate an interrupt once the data transmission is complete.RXNEIE  : This will enable an interrupt to be ge…

STM32 USART Pt1: Basic

Dont forget to check out the vidoe version of this tutorial on my YouTubechannel. 

The objective of my tutorials is not to divulge into the timing intricacies of any protocol. Only when it is necessary to program and setup the peripheral in the STM32 will I explain any low-level details of how the protocol operates.

One of the simpler communications peripherals to setup is the USART is UART mode. For this reason and because of its usefulness it proceeds GPIO. By the end of this tutorial you will learn to setup the USART in asynchronous mode thus making it a UART. Using the concepts learned here you will be able to write a reusable library for printing onto a serial monitor, that tutorial will be linked at the end of this tutorial.




The first order of business is to figure out what bus the USARTs are connected to. The image below demonstrates that UART1 is on the APB2 bus while all the rest of the USARTS are one APB1. This is a very important factor because those two busses have differe…

STM32 CRC for data validation

Suppose you are sending data packets to a critical device, the packets contain information instructing the device to continue operating, or to blow up in your face. Now imagine the data gets corrupted, by way of EMI or any form of interference. Now it is possible that the corruption has modified the command so that the device blows up in your face. It would be convenient if there was a way to prevent data corruption all together. I am not sure how one would prevent data corruption, but I know there are methods to verify whether the data has been corrupted or not, one such method is Cyclic Redundancy Check (CRC).
Implementing a CRC in software is not that hard. Using the images as reference below it is possible to implement the algorithm in plain C code. Though I will not do that here because this post is about the fact that STM32 microcontrollers (F0, F1, F2, F3, F4, L1) provide a hardware CRC engine that accomplishes the same task thousands of times faster then doing it in code. The s…